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D a t a S h e e t , Rev. 1.0, O c t . 2 0 0 4
HYS72T32000HR-[3.7/5]-A HYS72T64001HR-[3.7/5]-A HYS72T64020HR-[3.7/5]-A
240-Pin Registered DDR2 SDRAM Modules DDR2 SDRAM RDIMM SDRAM RoHS Compliant
Memory Products
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The information in this document is subject to change without notice. Edition 2004-10 Published by Infineon Technologies AG, St.-Martin-Strasse 53, 81669 Munchen, Germany (c) Infineon Technologies AG 2004. All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as a guarantee of characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office (www.infineon.com). Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.
D a t a S h e e t , Rev. 1.0, O c t . 2 0 0 4
HYS72T32000HR-[3.7/5]-A HYS72T64001HR-[3.7/5]-A HYS72T64020HR-[3.7/5]-A
240-Pin Registered DDR2 SDRAM Modules DDR2 SDRAM RDIMM SDRAM RoHS Compliant
Memory Products
Never
stop
thinking.
HYS72T32000HR-[3.7/5]-A, HYS72T64001HR-[3.7/5]-A, HYS72T64020HR-[3.7/5]-A Revision History: Previous Version: Page 23, 24 38,42 all all Rev. 1.0 Rev. 0.85 (2004-04-14) 2004-10
Subjects (major changes since last revision)
IDD currents are final
SPD Code Update Layout update Only green products included
We Listen to Your Comments Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to continuously improve the quality of this document. Please send your proposal (including a reference to this document) to: techdoc.mp@infineon.com
Template: mp_a4_v2.3_2004-01-14.fm
HYS72T[32/64]0[0/2][0/1]HR-[3.7/5]-A Registered Double-Data-Rate-Two SDRAM Modules
Table of Contents 1 1.1 1.2 2 2.1 3 3.1 3.2 4 4.1 5 6 7 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
IDD Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 On Die Termination (ODT) Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
IDD Specifications and Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 SPD Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Product Type Nomenclature (DDR2 DRAMs and DIMMs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Data Sheet
5
Rev. 1.0, 2004-10 02182004-UN2L-F13U
240-Pin Registered DDR2 SDRAM Modules DDR2 SDRAM
HYS72T32000HR-[3.7/5]-A HYS72T64001HR-[3.7/5]-A HYS72T64020HR-[3.7/5]-A
1
Overview
This chapter gives an overview of the 1.8 V 240-pin Registered DDR2 SDRAM Modules product family and describes its main characteristics.
1.1
* * * *
Features
* * * * * * * * Programmable CAS Latencies (3, 4 & 5), Burst Length (4 & 8) and Burst Type Auto Refresh (CBR) and Self Refresh All inputs and outputs SSTL_1.8 compatible Off-Chip Driver Impedance Adjustment (OCD) and On-Die Termination (ODT) Serial Presence Detect with E2PROM RDIMM Dimensions (nominal): 30,00 mm high, 133.35 mm wide Based on JEDEC standard reference layouts Raw Card "F", "G" & "H" RoHS Compliant Products1)
240-pin PC2-4200 and PC2-3200 DDR2 SDRAM memory modules for PC, Workstation and Server main memory applications One rank 32M x 72, 64M x 72 and two ranks 64M x 72 module organization and 32M x 8, 64M x 4 chip organization JEDEC standard Double-Data-Rate-Two Synchronous DRAMs (DDR2 SDRAM) with a single + 1.8 V ( 0.1 V) power supply Built with 256Mb DDR2 SDRAMs in P-TFBGA-60 chipsize packages.
Table 1
Performance -3.7 PC2-4200 4-4-4 @CL5 @CL4 @CL3 -5 PC2-3200 3-3-3 200 200 200 15 15 40 55 Units -- MHz MHz MHz ns ns ns ns
Product Type Speed Code Speed Grade max. Clock Frequency
min. RAS-CAS-Delay min. Row Precharge Time min. Row Active Time min. Row Cycle Time
fCK5 fCK4 fCK3 tRCD tRP tRAS tRC
266 266 200 15 15 45 60
1)RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and electronic equipment as defined in the directive 2002/95/EC issued by the European Parliament and of the Council of 27 January 2003. These substances include mercury, lead, cadmium, hexavalent chromium, polybrominated biphenyls and polybrominated biphenyl ethers.
Data Sheet
6
Rev. 1.0, 2004-10 02182004-UN2L-F13U
HYS72T[32/64]0[0/2][0/1]HR-[3.7/5]-A Registered Double-Data-Rate-Two SDRAM Modules
Overview
1.2
Description
using register devices and a PLL for the clock distribution. This reduces capacitive loading to the system bus, but adds one cycle to the SDRAM timing. Decoupling capacitors are mounted on the PCB board. The DIMMs feature serial presence detect based on a serial E2PROM device using the 2-pin I2C protocol. The first 128 bytes are programmed with configuration data and are write-protected; the second 128 bytes are available to the customer.
The INFINEON HYS72T[32/64]0[0/2][0/1]HR-[3.7/5]- A module family are Registered DIMM modules "RDIMMs" with 30,0 mm height based on DDR2 technology. DIMMs are available as ECC modules in 32M x 72 (256 MByte) and 64M x 72 (512 MByte organization and density, intended for mounting into 240-pin connector sockets. The memory array is designed with 256 Mb DoubleData-Rate-Two (DDR2) Synchronous DRAMs . All control and address signals are re-driven on the DIMM Table 2
Ordering Information for RoHS Compliant Products Compliance Code2) 256 MB 1Rx8 PC2-3200R-333-11-F1 512 MB 1Rx4 PC2-3200R-333-11-H1 512 MB 2Rx8 PC2-3200R-333-11-G1 256 MB 1Rx8 PC2-4200R-444-11-F1 512 MB 1Rx4 PC2-4200R-444-11-H1 512 MB 2Rx8 PC2-4200R-444-11-G1 Description 1 Rank, ECC 1 Rank, ECC 2 Rank, ECC 1 rank, ECC 1 rank, ECC 2 rank, ECC SDRAM Technology 256 Mbit (x8) 256 Mbit (x4) 256 Mbit (x8) 256 Mbit (x8) 256 Mbit (x4) 256 Mbit (x8)
Product Type1) PC2-3200 HYS72T32000HR-5-A HYS72T64001HR-5-A HYS72T64020HR-5-A PC2-4200 HYS72T32000HR-3.7-A HYS72T64001HR-3.7-A HYS72T64020HR-3.7-A
1) All part numbers end with a place code, designating the silicon die revision. Example: HYS72T32000HR-5-A, indicating Rev. "A" dies are used for DDR2 SDRAM components. For all INFINEON DDR2 module and component nomenclature see Chapter 7 of this data sheet. 2) The Compliance Code is printed on the module label and describes the speed grade, for example "PC2-4200R-444-11- F1", where 4200R means Registered DIMM modules with 4.26 GB/sec Module Bandwidth and "444-11" means Column Address Strobe (CAS) latency = 4, Row Column Delay (RCD) latency = 4 and Row Precharge (RP) latency = 4 using the latest JEDEC SPD Revision 1.1 and produced on the Raw Card "F"
Table 3 DIMM Density 256 MB 512 MB 512 MB
Address Format Module Organization 32M x72 64M x72 64M x72 Memory Ranks 1 1 2 ECC/ Non-ECC ECC ECC ECC # of SDRAMs 9 18 18 # of row/bank/columns bits Raw Card 14/2/10 14/2/11 14/2/10 F H G
Data Sheet
7
Rev. 1.0, 2004-10 02182004-UN2L-F13U
HYS72T[32/64]0[0/2][0/1]HR-[3.7/5]-A Registered Double-Data-Rate-Two SDRAM Modules
Overview
Table 4
Components on Modules 1) DRAM Components2) HYB18T256800AF-3.7 HYB18T256400AF-3.7 HYB18T256800AF-3.7 HYB18T256800AF-5 HYB18T256400AF-5 HYB18T256800AF-5 DRAM Density 256 Mbit 256 Mbit 256 Mbit 256 Mbit 256 Mbit 256 Mbit DRAM Organization 32M x 8 64M x 4 32M x 8 32M x 8 64M x 4 32M x 8
Product Type2) HYS72T32000HR-3.7-A HYS72T64001HR-3.7-A HYS72T64020HR-3.7-A HYS72T32000HR-5-A HYS72T64001HR-5-A HYS72T64020HR-5-A
2) Green Product
1) For a detailed description of all functionalities of the DRAM components on these modules see the component data sheet.
Data Sheet
8
Rev. 1.0, 2004-10 02182004-UN2L-F13U
HYS72T[32/64]0[0/2][0/1]HR-[3.7/5]-A Registered Double-Data-Rate-Two SDRAM Modules
Pin Configuration
2
Pin Configuration
explained in Table 6 and Table 7 respectively. The pin numbering is depicted in Figure 1.
The pin configuration of the Registered DDR2 SDRAM DIMM is listed by function in Table 5 (240 pins). The abbreviations used in columns Pin and Buffer Type are Table 5 Pin# Clock Signals 185 186 CK0 CK0 I I SSTL SSTL Pin Configuration of RDIMM Name Pin Type Buffer Type
Function
Clock Signal CK0, Complementary Clock Signal CK0 Note: The system clock inputs. All address and command lines are sampled on the cross point of the rising edge of CK and the falling edge of CK. A Delay Locked Loop (DLL) circuit is driven from the clock inputs and output timing for read operations is synchronized to the input clock. Clock Enables 1:0 Note: Activates the DDR2 SDRAM CK signal when HIGH and deactivates the CK signal when LOW. By deactivating the clocks, CKE0 initiates the Power Down Mode or the Self Refresh Mode. Note: 2-Ranks module Note: 1-Rank module Chip Select Rank 1:0 Note: Enables the associated DDR2 SDRAM command decoder when LOW and disables the command decoder when HIGH. When the command decoder is disabled, new commands are ignored but previous operations continue. Rank 0 is selected by S0; Rank 1 is selected by S1. The input signals also disable all outputs (except CKE and ODT) of the register(s) on the DIMM when both inputs are high. When S is HIGH, all register outputs (except CK, ODT and Chip select) remain in the previous state. Note: 2-Ranks module Note: 1-Rank module Row Address Strobe (RAS), Column Address Strobe (CAS), Write Enable (WE) Note: When sampled at the cross point of the rising edge of CK,and falling edge of CK, RAS, CAS and WE define the operation to be executed by the SDRAM. Register Reset Note: The RESET pin is connected to the RST pin on the register and to the OE pin on the PLL. When LOW, all register outputs will be driven LOW and the PLL clocks to the DRAMs and the register(s) will be set to low level. The PLL will remain synchronized with the input clock.
52 171
CKE0 CKE1
I I
SSTL SSTL
NC Control Signals 193 76 S0 S1
NC I I
-- SSTL SSTL
NC 192 74 73 18 RAS CAS WE RESET
NC I I I I
-- SSTL SSTL SSTL CMOS
Address Signals 71 190 Data Sheet BA0 BA1 I I SSTL SSTL Bank Address Bus 1:0 Note: Selects internal SDRAM memory bank 9 Rev. 1.0, 2004-10 02182004-UN2L-F13U
HYS72T[32/64]0[0/2][0/1]HR-[3.7/5]-A Registered Double-Data-Rate-Two SDRAM Modules
Pin Configuration Table 5 Pin# 54 Pin Configuration of RDIMM (cont'd) Name BA2 NC 188 183 63 182 61 60 180 58 179 177 70 57 176 196 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 AP A11 A12 A13 NC 174 A14 NC Pin Type I I I I I I I I I I I I I I I I I NC I NC Buffer Type SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL - SSTL - Address Signal 13 Note: modules based on x4, x8 Note: modules based on x16 Address Signal 14 Note: 2 Gbit based module Note: 1 Gbit based module or smaller Function Bank Address Bus 2 Note: greater than 512Mb DDR2 SDRAMS Note: less than 1Gb DDR2 SDRAMS Address Bus 12:0, Address Signal 10/AutoPrecharge Note: During a Bank Activate command cycle, defines the row address when sampled at the crosspoint of the rising edge of CK and falling edge of CK. During a Read or Write command cycle, defines the column address when sampled at the cross point of the rising edge of CK and falling edge of CK. In addition to the column address, AP is used to invoke autoprecharge operation at the end of the burst read or write cycle. If AP is HIGH, autoprecharge is selected and BA[1:0] defines the bank to be precharged. If AP is LOW, autoprecharge is disabled. During a Precharge command cycle, AP is used in conjunction with BA[1:0] to control which bank(s) to precharge. If AP is HIGH, all banks will be precharged regardless of the state of BA[1:0] inputs. If AP is LOW, then BA[1:0] are used to define which bank to precharge.
Data Sheet
10
Rev. 1.0, 2004-10 02182004-UN2L-F13U
HYS72T[32/64]0[0/2][0/1]HR-[3.7/5]-A Registered Double-Data-Rate-Two SDRAM Modules
Pin Configuration Table 5 Pin# Data Signals 3 4 9 10 122 123 128 129 12 13 21 22 131 132 140 141 24 25 30 31 143 144 149 150 33 34 39 40 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL Data Bus 63:0 Note: Data Input/Output pins Pin Configuration of RDIMM (cont'd) Name Pin Type Buffer Type Function
Data Sheet
11
Rev. 1.0, 2004-10 02182004-UN2L-F13U
HYS72T[32/64]0[0/2][0/1]HR-[3.7/5]-A Registered Double-Data-Rate-Two SDRAM Modules
Pin Configuration Table 5 Pin# 152 153 158 159 80 81 86 87 199 200 205 206 89 90 95 96 208 209 214 215 98 99 107 108 217 218 226 227 110 111 116 117 229 230 235 236 Pin Configuration of RDIMM (cont'd) Name DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 Pin Type I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Buffer Type SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL Function Data Bus 63:0
Data Sheet
12
Rev. 1.0, 2004-10 02182004-UN2L-F13U
HYS72T[32/64]0[0/2][0/1]HR-[3.7/5]-A Registered Double-Data-Rate-Two SDRAM Modules
Pin Configuration Table 5 Pin# 42 43 48 49 161 162 167 168 Data Strobe Bus 7 6 16 15 28 27 37 36 84 83 93 92 105 104 114 113 46 45 126 135 147 156 203 212 DQS0 DQS0 DQS1 DQS1 DQS2 DQS2 DQS3 DQS3 DQS4 DQS4 DQS5 DQS5 DQS6 DQS6 DQS7 DQS7 DQS8 DQS8 DQS9 NC DQS10 NC DQS11 NC DQS12 NC DQS13 NC DQS14 NC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O NC I/O NC I/O NC I/O NC I/O NC I/O NC SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL - SSTL - SSTL - SSTL - SSTL - SSTL - Note: x8 based DIMMs only Note: x4 based DIMMs Note: x8 based DIMMs only Note: x4 based DIMMs Note: x8 based DIMMs only Note: x4 based DIMMs Note: x8 based DIMMs only Note: x4 based DIMMs Note: x8 based DIMMs only Note: x4 based DIMMs Note: x8 based DIMMs only Note: x4 based DIMMs Data Strobes 17:0 Note: The data strobes, associated with one data byte, sourced with data transfers. In Write mode, the data strobe is sourced by the controller and is centered in the data window. In Read mode the data strobe is sourced by the DDR2 SDRAM and is sent at the leading edge of the data window. DQS signals are complements, and timing is relative to the crosspoint of respective DQS and DQS. If the module is to be operated in single ended strobe mode, all DQS signals must be tied on the system board to VSS through a 20 ohm to 10 Kohm resistor and DDR2 SDRAM mode registers programmed appropriately. Note: See block diagram for corresponding DQ signals Pin Configuration of RDIMM (cont'd) Name CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7 Pin Type I/O I/O I/O I/O I/O I/O I/O I/O Buffer Type SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL Function Check Bits 7:0 Note: Check Bit Input / Output pins Note: NC on Non-ECC module
Data Sheet
13
Rev. 1.0, 2004-10 02182004-UN2L-F13U
HYS72T[32/64]0[0/2][0/1]HR-[3.7/5]-A Registered Double-Data-Rate-Two SDRAM Modules
Pin Configuration Table 5 Pin# 224 233 165 125 134 146 155 202 211 223 232 164 125 134 146 155 202 211 223 232 164 EEPROM 120 SCL I CMOS Serial Bus Clock Note: This signal is used to clock data into and out of the SPD EEPROM. 119 SDA I/O OD Serial Bus Data Note: This is a bidirectional pin used to transfer data into or out of the SPD EEPROM. A resistor must be connected from SDA to VDDSPD on the motherboard to act as a pull-up. 239 240 101 Power Supplies 1 SA0 SA1 SA2 I I I CMOS CMOS CMOS Serial Address Select Bus 2:0 Note: These signals are tied at the system planar to either VSS or VDDSPD to configure the serial SPD EEPROM address range I/O Reference Voltage Note: Reference voltage for the SSTL-18 inputs. Pin Configuration of RDIMM (cont'd) Name DQS15 NC DQS16 NC DQS17 NC DQS9 DQS10 DQS11 DQS12 DQS13 DQS14 DQS15 DQS16 DQS17 DM0 DM1 DM2 DM3 DM4 DM5 DM6 DM7 DM8 Pin Type I/O NC I/O NC I/O NC I/O I/O I/O I/O I/O I/O I/O I/O I/O I I I I I I I I I Buffer Type SSTL - SSTL - SSTL - SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL Data Masks 7:0 Note: The data write masks, associated with one data byte. In Write mode, DM operates as a byte mask by allowing input data to be written if it is LOW but blocks the write operation if it is HIGH. In Read mode, DM lines have no effect. Note: x8 based module Function Note: x8 based DIMMs only Note: x4 based DIMMs Note: x8 based DIMMs only Note: x4 based DIMMs Note: x8 based DIMMs only Note: x4 based DIMMs Data Strobes 17:9 Note: x4 based module
VREF
AI
-
Data Sheet
14
Rev. 1.0, 2004-10 02182004-UN2L-F13U
HYS72T[32/64]0[0/2][0/1]HR-[3.7/5]-A Registered Double-Data-Rate-Two SDRAM Modules
Pin Configuration Table 5 Pin# 238 Pin Configuration of RDIMM (cont'd) Name Pin Type PWR Buffer Type - Function EEPROM Power Supply Note: Serial EEPROM positive power supply, wired to a separated power pin at the connector which supports from 1.7 Volt to 3.6 Volt. 51, 56, 62, 72, VDDQ 75, 78, 170, 175, 181, 191, 194 53, 59, 64, 67, 69, 172, 178, 184, 187, 189, 197 2, 5, 8, 11, 14, 17, 20, 23, 26, 29, 32, 35, 38, 41, 44, 47, 50, 65, 66, 79, 82, 85, 88, 91, 94, 97, 100, 103, 106, 109, 112, 115, 118, 121, 124, 127, 130, 133, 136, 139, 142, 145, 148, 151, 154, 157, 160, 163, 166, 169, 198, 201, 204, 207, 210, 213, 216, 219, 222, 225, 228, 231, 234, 237 Other Pins 19, 55, 68, 102, 137, 138, 173, 220, 221 195 77 NC NC - Not connected Pins not connected on Infineon RDIMM's On-Die Termination Control 1:0 Note: Asserts on-die termination for DQ, DM, DQS, and DQS signals if enabled via the DDR2 SDRAM mode register. Note: 2-Ranks module NC
Table 6 Abbreviation SSTL
VDDSPD
PWR
-
I/O Driver Power Supply Note: Power and ground for the DDR SDRAM
VDD
PWR
-
Power Supply Note: Power and ground for the DDR SDRAM
VSS
GND
-
Ground Plane Note: Power and ground for the DDR SDRAM
ODT0 ODT1
I I
SSTL SSTL
NC
-
Note: 1-Rank modules
Abbreviations for Buffer Type Description Serial Stub Terminated Logic (SSTL_18) CMOS Levels Open Drain. The corresponding pin has 2 operational states, active low and tristate, and allows multiple devices to share as a wire-OR.
CMOS
OD
Data Sheet
15
Rev. 1.0, 2004-10 02182004-UN2L-F13U
HYS72T[32/64]0[0/2][0/1]HR-[3.7/5]-A Registered Double-Data-Rate-Two SDRAM Modules
Pin Configuration
Table 7 Abbreviation I O I/O AI PWR GND NU NC Abbreviations for Pin Type Description Standard input-only pin. Digital levels. Output. Digital levels. I/O is a bidirectional input/output signal. Input. Analog levels. Power Ground Not Usable Not Connected
Data Sheet
16
Rev. 1.0, 2004-10 02182004-UN2L-F13U
HYS72T[32/64]0[0/2][0/1]HR-[3.7/5]-A Registered Double-Data-Rate-Two SDRAM Modules
Pin Configuration
VREF DQ0 V SS DQS0 DQ2 V SS DQ9 DQS1 V SS NC DQ10 V SS DQ17 DQS2 V SS DQ19 DQ24 V SS DQS3 DQ26 V SS CB1 DQS8 V SS CB3 V DDQ V DD NC A11 V DD A4 A2
- Pin 001 - Pin 003 - Pin 005 - Pin 007 - Pin 009 - Pin 011 - Pin 013 - Pin 015 - Pin 017 - Pin 019 - Pin 021 - Pin 023 - Pin 025 - Pin 027 - Pin 029 - Pin 031 - Pin 033 - Pin 035 - Pin 037 - Pin 039 - Pin 041 - Pin 043 - Pin 045 - Pin 047 - Pin 049 - Pin 051 - Pin 053 - Pin 055 - Pin 057 - Pin 059 - Pin 061 - Pin 063
V SS DQ1 DQS0 V SS DQ3 DQ8 V SS DQS1 V SS DQ11 DQ16 V SS DQS2 DQ18 V SS DQ25 DQS3 V SS DQ27 CB0 V SS DQS8 CB2 V SS CKE0
- Pin 002 - Pin 004 - Pin 006 - Pin 008 - Pin 010 - Pin 012 - Pin 014 - Pin 016 - Pin 020 - Pin 022 - Pin 024
Pin 122 - DQ4 Pin 124 - V SS Pin 126 - NC/DQS9 Pin 128 - DQ6 Pin 130 - V SS Pin 132 - DQ13 Pin 134 - DM1/DQS10 Pin 136 - V SS Pin 138 - NC Pin 140 - DQ14 Pin 142 - V SS Pin 144 - DQ21
Pin 121 - V SS Pin 123 - DQ5 Pin 125 - DM0/DQS9 Pin 127 - V SS Pin 129 - DQ7 Pin 131 - DQ12 Pin 133 - V SS Pin 135 - NC/DQS10 Pin 137 - NC Pin 139 - V SS Pin 141 - DQ15 Pin 143 - DQ20 - V SS - NC/DQS11 - DQ22 - V SS - DQ29 - DM3/DQS12 - V SS - DQ31 - CB4 - V SS - NC/DQS17 - CB6 - V SS - NC/CKE1 - NC - V DDQ - A9 - A8 - V DDQ - A1
RESET - Pin 018
FRONTSIDE
- Pin 030 - Pin 032 - Pin 034 - Pin 036 - Pin 038 - Pin 040 - Pin 042 - Pin 044 - Pin 046 - Pin 048 - Pin 050
- Pin 052 NC/BA2 - Pin 054 - Pin 056 V DDQ A7 A5 V DDQ V DD - Pin 058 - Pin 060 - Pin 062 - Pin 064
BACKSIDE
- Pin 026 - Pin 028
Pin 145 Pin 146 - DM2/DQS11 Pin 147 - V SS Pin 148 Pin 149 Pin 150 - DQ23 Pin 151 - DQ28 Pin 152 Pin 153 Pin 154 - V SS Pin 155 Pin 156 - NC/DQS12 Pin 157 Pin 158 - DQ30 Pin 159 Pin 160 - V SS Pin 161 Pin 162 - CB5 Pin 163 Pin 164 - DM8/DQS17 Pin 165 Pin 166 - V SS Pin 167 Pin 168 - CB7 Pin 169 Pin 170 - V DDQ Pin 171 Pin 172 - V DD Pin 173 Pin 174 - NC/A14 Pin 175 Pin 176 - A12 Pin 177 Pin 178 - V DD Pin 179 Pin 180 - A6 Pin 181 Pin 182 - A3 Pin 183 Pin 184 - V DD
V SS V DD V DD BA0 WE V DDQ V SS DQ33 DQS4 V SS DQ35 DQ40 V SS DQS5 DQ42 V SS DQ49 SA2 V SS DQS6 DQ50 V SS DQ57 DQS7 V SS DQ59 SDA
- Pin 065 - Pin 067 - Pin 069 - Pin 071 - Pin 073 - Pin 075 - Pin 079 - Pin 081 - Pin 083 - Pin 085 - Pin 087 - Pin 089 - Pin 091 - Pin 093 - Pin 095 - Pin 097 - Pin 099 - Pin 101 - Pin 103 - Pin 105 - Pin 107 - Pin 109 - Pin 111 - Pin 113 - Pin 115 - Pin 117 - Pin 119
V SS
- Pin 066
NC - Pin 068 A10/AP - Pin 070 - Pin 072 V
DDQ
Pin 186 - CK0 Pin 188 - A0 Pin 190 - BA1 Pin 192 - RAS Pin 194 - V DDQ Pin 196 - NC/A13 Pin 198 - V SS
Pin 185 - CK0 Pin 187 - V DD Pin 189 - V DD Pin 191 - V DDQ Pin 193 - S0 Pin 195 - ODT0 Pin 197 - V DD - DQ36 - V SS - NC/DQS13 - DQ38 - V SS - DQ45 - DM5/DQS14 - V SS - DQ47 - DQ52 - V SS - NC - DM6/DQS15 - V SS - DQ55 - DQ60 - V SS - NC/DQS16 - DQ62 V SS SA0 MPPT0170
CAS NC/S1 V DDQ DQ32 V SS DQS4 DQ34 V SS DQ41 DQS5 V SS DQ43 DQ48 V SS NC DQS6 V SS DQ51 DQ56 V SS DQS7 DQ58 V SS SCL
NC/ODT1 - Pin 077
- Pin 074 - Pin 076 - Pin 078 - Pin 080 - Pin 082 - Pin 084 - Pin 086 - Pin 088 - Pin 090 - Pin 092 - Pin 094 - Pin 096 - Pin 098 - Pin 100 - Pin 102 - Pin 104 - Pin 106 - Pin 108 - Pin 110 - Pin 112 - Pin 114 - Pin 116 - Pin 118 - Pin 120
Pin 199 Pin 200 - DQ37 Pin 201 Pin 202 - DM4/DQS13 Pin 203 Pin 204 - V SS Pin 205 Pin 206 - DQ39 Pin 207 Pin 208 - DQ44 Pin 209 Pin 210 - V SS Pin 211 Pin 212 - NC/DQS14 Pin 213 Pin 214 - DQ46 Pin 215 Pin 216 - V SS Pin 217 - DQ53 Pin 218 Pin 219 Pin 220 - NC Pin 221 Pin 222 - V SS Pin 223 Pin 224 - NC/DQS15 Pin 225 Pin 226 - DQ54 Pin 227 Pin 228 - V SS Pin 229 Pin 230 - DQ61 Pin 231 Pin 232 - DM7/DQS16 Pin 233 Pin 234 - V SS Pin 235 Pin 236 - DQ63 Pin 237 Pin 238 VDDSPD Pin 239 Pin 240 SA1
Figure 1
Pin Configuration for RDIMM (240 pins)
Data Sheet
17
Rev. 1.0, 2004-10 02182004-UN2L-F13U
HYS72T[32/64]0[0/2][0/1]HR-[3.7/5]-A Registered Double-Data-Rate-Two SDRAM Modules
Pin Configuration
2.1
&. &. 5(6(7 6 %$ %$Q $ $Q 5$6 &$6 :( &.( 2'7 3&. 3&. 5(6(7 56 '46 '46 '0'46 '46 '4 '4 '4 '4 '4 '4 '4 '4 '46 '46 '0'46 '46 '4 '4 '4 '4 '4 '4 '4 '4 '46 '46 '0'46 '46 '4 '4 '4 '4 '4 '4 '4 '4
Block Diagrams
3// 2( 5 ( * , 6 7 ( 5 3&.3&. 3&. 3&. 3&.3&. 3&. 3&. 3&. 3&. 56 5%$5%$Q 5$5$Q 55$6 5&$6 5:( 5&.( 52'7 &. 6'5$0V '' &. 6'5$0V '' &. 5HJLVWHU &. 5HJLVWHU 9''63' 9''9''4 95() 966 9'' 63' ((3520 ( 9''9''4 6'5$0V ' ' 95() 6'5$0V ' ' 966 6'5$0V ' '
&6 6'5$0V '' %$%$Q 6'5$0V '' $$Q 6'5$0V '' 5$6 6'5$0V '' &$6 6'5$0V '' :( 6'5$0V '' &.( 6'5$0V '' 2'7 6'5$0V ''
6&/ 6'$ 6$ 6$ 6$ 966 ' '46 '46 '0'46 '46 '4 '4 '4 '4 '4 '4 '4 '4 ' '46 '46 '0'46 '46 '4 '4 '4 '4 '4 '4 '4 '4 ' '46 '46 '0'46 '46 &% &% &% &% &% &% &% &%
6&/ 6'$ $ $ $ :3
(
'46 '46 '05'46 185'46 ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,2
&6
' '46 '46 '0'46 '46 '4 '4 '4 '4 '4 '4 '4 '4 ' '46 '46 '0'46 '46 '4 '4 '4 '4 '4 '4 '4 '4 ' '46 '46 '0'46 '46 '4 '4 '4 '4 '4 '4 '4 '4
'46 '46 '05'46 185'46 ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,2
&6
'46 '46 '05'46 185'46 ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,2
&6
'
&6 '46 '46 '05'46 185'46 ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,2 '46 '46 '05'46 185'46 ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,2 &6
&6 '46 '46 '05'46 185'46 ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,2 '46 '46 '05'46 185'46 ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,2 &6
&6 '46 '46 '05'46 185'46 ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,2 '46 '46 '05'46 185'46 ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,2 &6
'
'
03%7
Figure 2 Notes
Block Diagram Raw Card F RDIMM (x72, 1Rank, x8) 2. S0 connects to DCS and VDD connects to CSR on the register.
1. Unless otherwise noted, resistors are 22 5 %
Data Sheet
18
Rev. 1.0, 2004-10 02182004-UN2L-F13U
HYS72T[32/64]0[0/2][0/1]HR-[3.7/5]-A Registered Double-Data-Rate-Two SDRAM Modules
Pin Configuration
&. &. 5(6(7 6 6 %$ %$Q $ $Q 5$6 &$6 :( &.( &.( 2'7 2'7 3&. 3&. 5(6(7 56 56 '46 '46 '0'46 '46 '4 '4 '4 '4 '4 '4 '4 '4 '46 '46 '0'46 '46 '4 '4 '4 '4 '4 '4 '4 '4 '46 '46 '0'46 '46 '4 '4 '4 '4 '4 '4 '4 '4 '46 '46 '0'46 '46 '4 '4 '4 '4 '4 '4 '4 '4
3// 2( 5 ( * , 6 7 ( 5
3&.3&. 3&. 3&. 3&.3&. 3&. 3&. 3&. 3&. 56 56 5%$5%$Q 5$5$Q 55$6 5&$6 5:( 5&.( 5&.( 52'7 52'7
&. 6'5$0V '' &. 6'5$0V '' &. 5HJLVWHU &. 5HJLVWHU
9''63' 9''9''4 95() 966
9'' 63' ((3520 ( 9''9''4 6'5$0V '' 95() 6'5$0V '' 966 6'5$0V ''
&6 6'5$0V '' &6 6'5$0V '' %$%$Q 6'5$0V '' $$Q 6'5$0V '' 5$6 6'5$0V '' &$6 6'5$0V '' :( 6'5$0V '' &.( 6'5$0V '' &.( 6'5$0V '' 2'7 6'5$0V '' 2'7 6'5$0V ''
'46 '46 '0'46 '46 '4 '4 '4 '4 '4 '4 '4 '4 '46 '46 '0'46 '46 '4 '4 ( '4 '4 '4 '4 '4 '4 '46 '46 '0'46 '46 '4 '4 '4 '4 '4 '4 '4 '4
&6 '46 '46 '05'46 185'46 ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,2 '46 '46 '05'46 185'46 ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,2 &6
'
&6 '46 '46 '05'46 185'46 ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,2 '46 '46 '05'46 185'46 ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,2 &6
'
'46 '46 '05'46 185'46 ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,2
&6
'
'46 '46 '05'46 185'46 ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,2 '
&6
'
'
'
&6 '46 '46 '05'46 185'46 ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,2 '46 '46 '05'46 185'46 ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,2 &6
&6 '46 '46 '05'46 185'46 ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,2 '46 '46 '05'46 185'46 ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,2 &6
6&/ 6'$ 6$ 6$ 6$ 966 '
6&/ 6'$ $ $ $ :3
&6 '46 '46 '05'46 185'46 ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,2 '46 '46 '05'46 185'46 ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,2 &6
'
&6 '46 '46 '05'46 185'46 ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,2 '46 '46 '05'46 185'46 ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,2 &6
'
'
' '46 '46 '0'46 '46 '4 '4 '4 '4 '4 '4 '4 '4 ' '46 '46 '0'46 '46 &% &% &% &% &% &% &% &%
'
'
&6 '46 '46 '05'46 185'46 ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,2
'
&6 '46 '46 '05'46 185'46 ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,2
&6 '46 '46 '05'46 185'46 ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,2
'
&6 '46 '46 '05'46 185'46 ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,2
'
03%7
Figure 3 Notes
Block Diagram Raw Card G RDIMM (x72, 2Ranks, x8) 2. RS0 and RS1 alternate between the back and front sides of the DIMM.
1. Unless otherwise noted, resistors are 22 5 %
Data Sheet
19
Rev. 1.0, 2004-10 02182004-UN2L-F13U
HYS72T[32/64]0[0/2][0/1]HR-[3.7/5]-A Registered Double-Data-Rate-Two SDRAM Modules
Pin Configuration
)
&. &. 5(6(7 6 %$ %$Q $ $Q 5$6 &$6 :( &.( 2'7 3&. 3&. 5(6(7 56 '46 '46 '4 '4 '4 '4 966 '46 '46 '4 '4 '4 '4 966 '46 '46 '4 '4 '4 '4 966 '46 '46 '4 '4 '4 '4 966 '46 '46 '4 '4 '4 '4 966 '46 '46 '4 '4 '4 '4 966
3// 2( 5 ( * , 6 7 ( 5
3&.3&. 3&. 3&. 3&.3&. 3&. 3&. 3&. 3&. 56 5%$5%$Q 5$5$Q 55$6 5&$6 5:( 5&.( 52'7
&. &. &. &.
6'5$0V '' 6'5$0V '' 5HJLVWHU 5HJLVWHU
9''63' 9''9''4 95() 966
9'' 63' ((3520 ( 9''9''4 6'5$0V '' 95() 6'5$0V '' 966 6'5$0V ''
&6 6'5$0V '' %$%$Q 6'5$0V '' $$Q 6'5$0V '' 5$6 6'5$0V '' &$6 6'5$0V '' :( 6'5$0V '' &.( 6'5$0V '' 2'7 6'5$0V ''
6&/ 6'$ 6$ 6$ 6$ 966 ' '46 '46 '4 '4 '4 '4 966 ' '46 '46 '4 '4 '4 '4 966 ' '46 '46 '4 '4 '4 '4 966 ' '46 '46 '4 '4 '4 '4 966 ' '46 '46 '4 '4 '4 '4 966 ' '46 '46 &% &% &% &% 966
6&/ 6'$ $ $ $ :3
(
'46 '46 ,2 ,2 ,2 ,2 '0 '46 '46 ,2 ,2 ,2 ,2 '0 '46 '46 ,2 ,2 ,2 ,2 '0 '46 '46 ,2 ,2 ,2 ,2 '0 '46 '46 ,2 ,2 ,2 ,2 '0 '46 '46 ,2 ,2 ,2 ,2 '0
&6
' '46 '46 '4 '4 '4 '4 966 ' '46 '46 '4 '4 '4 '4 966 ' '46 '46 &% &% &% &% 966 ' '46 '46 '4 '4 '4 '4 966 ' '46 '46 '4 '4 '4 '4 966 ' '46 '46 '4 '4 '4 '4 966 '46 '46 ,2 ,2 ,2 ,2 '0 '46 '46 ,2 ,2 ,2 ,2 '0 '46 '46 ,2 ,2 ,2 ,2 '0 '46 '46 ,2 ,2 ,2 ,2 '0 '46 '46 ,2 ,2 ,2 ,2 '0 '46 '46 ,2 ,2 ,2 ,2 '0
&6
'46 '46 ,2 ,2 ,2 ,2 '0 '46 '46 ,2 ,2 ,2 ,2 '0 '46 '46 ,2 ,2 ,2 ,2 '0 '46 '46 ,2 ,2 ,2 ,2 '0 '46 '46 ,2 ,2 ,2 ,2 '0 '46 '46 ,2 ,2 ,2 ,2 '0
&6
'
&6
&6
&6
'
&6
&6
&6
'
&6
&6
&6
'
&6
&6
&6
'
&6
&6
&6
'
03%7
Figure 4 Notes
Block Diagram Raw Card H RDIMM (x72, 1Rank, x4) 3. CSR of register1 and DCS of register2 connects to VDD. 4. RESET, PCK7 and PCK7 connect to both registers.
1. Unless otherwise noted, resistors are 22 5 % 2. S0 connects to DCS of register1 and CSR of register2.
Data Sheet
20
Rev. 1.0, 2004-10 02182004-UN2L-F13U
HYS72T[32/64]0[0/2][0/1]HR-[3.7/5]-A Registered Double-Data-Rate-Two SDRAM Modules
IDD Specifications and Conditions
3
Table 8 Parameter
IDD Specifications and Conditions
IDD Measurement Conditions1)2)3)4)5)6)7)8)
Symbol
Operating Current 0 One bank Active - Precharge; tCK = tCK.MIN, tRC = tRC.MIN, tRAS = tRAS.MIN, CKE is HIGH, CS is HIGH between valid commands. Address and control inputs are SWITCHING, Databus inputs are SWITCHING.
IDD0
Operating Current 1 IDD1 One bank Active - Read - Precharge; IOUT = 0 mA, BL = 4, tCK = tCK.MIN, tRC = tRC.MIN, tRAS = tRAS.MIN, tRCD = tRCD.MIN, AL = 0, CL = CL.MIN; CKE is HIGH, CS is HIGH between valid commands. Address and control inputs are SWITCHING, Databus inputs are SWITCHING. Precharge Standby Current All banks idle; CS is HIGH; CKE is HIGH; tCK = tCK.MIN; Other control and address inputs are SWITCHING, Data bus inputs are SWITCHING. Precharge Power-Down Current Other control and address inputs are STABLE, Data bus inputs are FLOATING.
IDD2N IDD2P
Precharge Quiet Standby Current IDD2Q All banks idle; CS is HIGH; CKE is HIGH; tCK = tCK.MIN; Other control and address inputs are STABLE, Data bus inputs are FLOATING. Active Power-Down Current All banks open; tCK = tCK.MIN, CKE is LOW; Other control and address inputs are STABLE, Data bus inputs are FLOATING. MRS A12 bit is set to LOW (Fast Power-down Exit); Active Power-Down Current All banks open; tCK = tCK.MIN, CKE is LOW; Other control and address inputs are STABLE, Data bus inputs are FLOATING. MRS A12 bit is set to HIGH (Slow Power-down Exit); Active Standby Current Burst Read: All banks open; Continuous burst reads; BL = 4; AL = 0, CL = CLMIN; tCK = tCK.MIN; tRAS = tRAS.MAX, tRP = tRP.MIN; CKE is HIGH, CS is HIGH between valid commands. Address inputs are SWITCHING; Data Bus inputs are SWITCHING; IOUT = 0 mA. Operating Current Burst Read: All banks open; Continuous burst reads; BL = 4; AL = 0, CL = CLMIN; tCK = tCK.MIN; tRAS = tRAS.MAX., tRP = tRP.MIN; CKE is HIGH, CS is HIGH between valid commands. Address inputs are SWITCHING; Data Bus inputs are SWITCHING; IOUT = 0 mA.
IDD3P(0) IDD3P(1) IDD3N
IDD4R
Operating Current IDD4W Burst Write: All banks open; Continuous burst writes; BL = 4; AL = 0, CL = CLMIN; tCK = tCK.MIN; tRAS = tRAS.MAX., tRP = tRP.MAX; CKE is HIGH, CS is HIGH between valid commands. Address inputs are SWITCHING; Data Bus inputs are SWITCHING; Burst Refresh Current IDD5B tCK = tCK.MIN., Refresh command every tRFC = tRFC.MIN interval, CKE is HIGH, CS is HIGH between valid commands, Other control and address inputs are SWITCHING, Data bus inputs are SWITCHING. Distributed Refresh Current IDD5D tCK = tCK.MIN, Refresh command every tRFC = tREFI interval, CKE is LOW and CS is HIGH between valid commands, Other control and address inputs are SWITCHING, Data bus inputs are SWITCHING.
Data Sheet
21
Rev. 1.0, 2004-10 02182004-UN2L-F13U
HYS72T[32/64]0[0/2][0/1]HR-[3.7/5]-A Registered Double-Data-Rate-Two SDRAM Modules
IDD Specifications and Conditions Table 8 Parameter Self-Refresh Current CKE 0.2 V; external clock off, CK and CK at 0 V; Other control and address inputs are FLOATING, Data bus inputs are FLOATING. RESET is LOW. IDD6 current values are guaranteed up to TCASE of 85 C max.
IDD Measurement Conditions1)2)3)4)5)6)7)8)
Symbol
IDD6
All Bank Interleave Read Current IDD7 All banks are being interleaved at minimum tRC without violating tRRD using a burst length of 4. Control and address bus inputs are STABLE during DESELECTS. IOUT = 0 mA.
1)
VDDQ = 1.8 V 0.1 V; VDD = 1.8 V 0.1 V 2) IDD specifications are tested after the device is properly initialized and IDD parameter are specified with ODT disabled. 3) Definitions for IDD: LOW is defined as VIN VIL(ac).MAX, HIGH is defined as VIN VIH(ac).MIN
STABLE is defined as: inputs are stable at a HIGH or LOW level FLOATING is defined as: inputs are VREF = VDDQ /2 SWITCHING is defined as: inputs are changing between HIGH and LOW every other clock (once per 2 cycles) for address and control signals, and inputs changing between HIGH and LOW every other data transfer (once per cycle) for DQ signals not including mask or strobes.
4)
IDD1, IDD4R and IDD7 current measurements are defined with the outputs disabled (IOUT = 0 mA). To achieve this on module level the output buffers can be disabled using an EMRS(1) (Extended Mode Register Command) by setting A12 bit to HIGH.
5) For two rank modules: for all active current measurements the other rank is in Precharge Power-Down Mode IDD2P 6) RESET signal is HIGH for all currents, except for IDD6 (Self Refresh) 7) All current measurements includes Register and PLL current consumption 8) For details and notes see the relevant INFINEON component data sheet
Data Sheet
22
Rev. 1.0, 2004-10 02182004-UN2L-F13U
HYS72T[32/64]0[0/2][0/1]HR-[3.7/5]-A Registered Double-Data-Rate-Two SDRAM Modules
IDD Specifications and Conditions
Table 9
IDD Specification for HYS72T[32000/64001/64020]HR-3.7-A
HYS72T32000HR-3.7-A HYS72T64001HR-3.7-A HYS72T64020HR-3.7-A Unit Notes1)
Product Type Organization
256MB x72 1 Rank -3.7
512MB x72 1 Rank -3.7 Max. 1490 1580 1130 570 950 1130 790 572 1760 2030 2030 110 70 2930
512MB x72 2 Ranks -3.7 Max. 860 910 960 400 780 680 620 402 1000 1130 1130 90 70 1580 mA mA mA mA mA mA mA mA mA mA mA mA mA mA
2) 2) 3) 3) 3) 3) 3) 3) 2) 2) 2) 3) 3) 2)
Symbol
Max. 830 870 650 370 560 650 470 366 960 1100 1100 50 40 1550
IDD0 IDD1 IDD2N IDD2P IDD2Q IDD3N IDD3P(MRS= 0) IDD3P(MRS= 1) IDD4R IDD4W IDD5B IDD5D IDD6 IDD7
1) Module IDD is calculated on the basis of component IDD and currents includes Registers and PLL. ODT disabled. IDD1, IDD4R and IDD7 are defined with the outputs disabled. 2) The other rank is in IDD2P Precharge Power-Down Standby Current mode 3) Both ranks are in the same IDD mode
Data Sheet
23
Rev. 1.0, 2004-10 02182004-UN2L-F13U
HYS72T[32/64]0[0/2][0/1]HR-[3.7/5]-A Registered Double-Data-Rate-Two SDRAM Modules
IDD Specifications and Conditions
Table 10
IDD Specification for HYS72T[32000/64001/64020]HR-5-A
HYS72T32000HR-5-A HYS72T64001HR-5-A HYS72T64020HR-5-A Unit Notes1)
Product Type Organization
256MB x72 1 Rank -5
512MB x72 1 Rank -5 Max. 1310 1400 910 480 770 950 640 477 1490 1670 1850 110 70 2660
512MB x72 2 Ranks -5 Max. 760 810 780 350 640 580 510 347 850 940 1030 90 70 1440 mA mA mA mA mA mA mA mA mA mA mA mA mA mA
2) 2) 3) 3) 3) 3) 3) 3) 2) 2) 2) 3) 3) 2)
Symbol
Max. 730 770 530 310 460 550 390 311 820 910 1000 50 40 1400
IDD0 IDD1 IDD2N IDD2P IDD2Q IDD3N IDD3P(MRS= 0) IDD3P(MRS= 1) IDD4R IDD4W IDD5B IDD5D IDD6 IDD7
1) Module IDD is calculated on the basis of component IDD and currents includes Registers and PLL. ODT disabled. IDD1, IDD4R and IDD7 are defined with the outputs disabled. 2) The other rank is in IDD2P Precharge Power-Down Standby Current mode 3) Both ranks are in the same IDD mode
Data Sheet
24
Rev. 1.0, 2004-10 02182004-UN2L-F13U
HYS72T[32/64]0[0/2][0/1]HR-[3.7/5]-A Registered Double-Data-Rate-Two SDRAM Modules
IDD Specifications and Conditions
3.1
IDD Test Conditions
IDD Measurement Test Conditions
Symbol -3.7 4 3.75 15 60 7.5 10 45 70000 15 75 7.8 -5 3 5 15 55 7.5 10 40 70000 15 75 7.8 Unit PC2-4200-4-4-4 PC2-3200-3-3-3
For testing the IDD parameters, the following timing parameters are used: Table 11 Parameter CAS Latency
CL(IDD) Clock Cycle Time tCK(IDD) Active to Read or Write delay tRCD(IDD) Active to Active / Auto-Refresh command period tRC(IDD) 1) Active bank A to Active bank B command delay x8 tRRD(IDD) 2) x16 tRRD(IDD) Active to Precharge Command tRAS.MIN(IDD) tRAS.MAX(IDD) Precharge Command Period tRP(IDD) Auto-Refresh to Active / Auto-Refresh command period tRFC(IDD) Average periodic Refresh interval tREFI
1) For modules based on x8 components 2) For modules based on x16 components
tCK
ns ns ns ns ns ns ns ns ns s
3.2
On Die Termination (ODT) Current
current consumption for any terminated input pin, depends on the input pin is in tri-state or driving 0 or 1, as long a ODT is enabled during a given period of time.
The ODT function adds additional current consumption to the DDR2 SDRAM when enabled by the EMRS(1). Depending on address bits A[6,2] in the EMRS(1) a "weak" or "strong" termination can be selected. The Table 12 Parameter ODT current per terminated pin
Symbol Min. 5 2.5 10 5
Typ. 6 3 12 6
Max. 7.5 3.75 15 7.5
Unit mA/DQ mA/DQ mA/DQ mA/DQ
EMRS(1) State A6 = 0, A2 = 1 A6 = 1, A2 = 0 A6 = 0, A2 = 1 A6 = 1, A2 = 0
Enabled ODT current per DQ IODTO ODT is HIGH; Data Bus inputs are FLOATING Active ODT current per DQ ODT is HIGH; worst case of Data Bus inputs are STABLE or SWITCHING.
IODTT
Data Sheet
25
Rev. 1.0, 2004-10 02182004-UN2L-F13U
HYS72T[32/64]0[0/2][0/1]HR-[3.7/5]-A Registered Double-Data-Rate-Two SDRAM Modules
Electrical Characteristics
4
4.1
Table 13 Parameter
Electrical Characteristics
Operating Conditions
Absolute Maximum Ratings Symbol Values Min. Max. 2.3 2.3 2.3 95 V V V % - 0.5 - 1.0 - 0.5 5 Unit Note/Test Condition
1) 1) 1) 1)
Voltage on any pins relative to VSS Voltage on VDD relative to VSS Voltage on VDD Q relative to VSS Storage Humidity (without condensation)
VIN, VOUT VDD VDDQ HSTG
1) Stresses greater than those listed may cause permanent damage to the device. This is a stress rating only, and device functional operation at or above the conditions indicated is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability
Table 14 Parameter
Operating Conditions Symbol Values Min. Max. +55 +95 +100 +105 90 C C C kPa %
5) 1)2)3)4)
Unit
Notes
DIMM Module Operating Temperature Range (ambient) DRAM Component Case Temperature Range Storage Temperature Barometric Pressure (operating & storage) Operating Humidity (relative)
TOPR TCASE TSTG
PBar
0 0 - 50 +69 10
HOPR
1) DRAM Component Case Temperature is the surface temperature in the center on the top side of any of the DRAMs. 2) Within the DRAM Component Case Temperature range all DRAM specification will be supported. 3) Above 85 C DRAM case temperature the Auto-Refresh command interval has to be reduced to tREFI = 3.9 s. 4) Self-Refresh period is hard-coded in the DRAMs and therefore it is imperative that the system ensures the DRAM is below 85 C case temperature before initiating self-refresh operation. 5) Up to 3000 m
Table 15 Parameter
Supply Voltage Levels and DC Operating Conditions Symbol Values Min. Nom. 1.8 1.8 0.5 x VDDQ -- -- -- Max. 1.9 1.9 0.51 x VDDQ 3.6 V V V V V V A
3) 1) 2)
Unit
Notes
Device Supply Voltage Output Supply Voltage Input Reference Voltage SPD Supply Voltage DC Input Logic High DC Input Logic Low In / Output Leakage Current
VDD VDDQ VREF VDDSPD VIH (DC) VIL (DC) IL
1.7 1.7 0.49 x VDDQ 1.7
VREF + 0.125
- 0.30 -5
VDDQ + 0.3 VREF - 0.125
5
1) Under all conditions, VDDQ must be less than or equal to VDD 2) Peak to peak AC noise on VREF may not exceed 2% VREF (DC).VREF is also expected to track noise variations in VDDQ. 3) Input voltage for any connector pin under test of 0 V VIN VDDQ + 0.3 V; all other pins at 0 V. Current is per pin
Data Sheet
26
Rev. 1.0, 2004-10 02182004-UN2L-F13U
HYS72T[32/64]0[0/2][0/1]HR-[3.7/5]-A Registered Double-Data-Rate-Two SDRAM Modules
Electrical Characteristics
Table 16
Speed Grade Definition Speed Bins DDR2-533C -3.7 4-4-4 Symbol @ CL = 3 @ CL = 4 @ CL = 5 Min. 5 3.75 3.75 45 60 15 15 Max. 8 8 8 70000 -- -- -- DDR2-400B -5 3-3-3 Min. 5 5 5 40 55 15 15 Max. 8 8 8 70000 -- -- -- Unit Notes
Speed Grade IFX Sort Name CAS-RCD-RP latencies Parameter Clock Frequency
tCK
-- ns ns ns ns ns ns ns
1)2)3)4) 1)2)3)4) 1)2)3)4) 1)2)3)4)5) 1)2)3)4) 1)2)3)4) 1)2)3)4)
RAS-CAS-Delay Row Precharge Time Row Active Time Row Cycle Time
tCK tCK tCK tRAS tRC tRCD tRP
1) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode. . Timings are further guaranteed for normal OCD drive strength (EMRS(1) A1 = 0) only. 2) The CK CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS, input reference level is the crosspoint when in differential strobe mode 3) Inputs are not recognized as valid until recognized as low. 5)
VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is
4) The output timing reference voltage level is VTT.
tRAS.MAX is calculated from the maximum amount of time a DDR2 device can operate without a refresh command which is equal to 9 x tREFI.
Timing Parameter by Speed Grade - DDR2-400B & DDR2-533C Symbol -3.7 DDR2-533 4-4-4 Min. Max. +500 -- 0.55 -- 0.55 -- -- -- -- -- +450 -- -500 2 0.45 3 0.45 WR + tRP -5 DDR2-400 3-3-3 Min. -600 2 0.45 3 0.45 WR + tRP Max. +600 -- 0.55 -- 0.55 -- ps Unit Notes1)
Table 17 Parameter
DQ output access time from CK / CK tAC CAS A to CAS B command period CK, CK high-level width CKE minimum high and low pulse width CK, CK low-level width Auto-Precharge write recovery + precharge time
tCCD tCH tCKE tCL tDAL
tCK tCK tCK tCK tCK
ns ps ps
Minimum time clocks remain ON after tDELAY CKE asynchronously drops LOW DQ and DM input hold time (differential data strobe) DQ and DM input hold time (single ended data strobe) DQ and DM input pulse width (each input) DQS input low (high) pulse width (write cycle)
tIS + tCK + tIH
tIS + tCK + -- tIH
275 25 0.35 -500 0.35 -- -- -- +500 --
tDH(base) 225 tDH1(base) -25 tDIPW
0.35 -450 0.35
tCK
ps
DQS output access time from CK / CK tDQSCK
tDQSL,H
tCK
Data Sheet
27
Rev. 1.0, 2004-10 02182004-UN2L-F13U
HYS72T[32/64]0[0/2][0/1]HR-[3.7/5]-A Registered Double-Data-Rate-Two SDRAM Modules
Electrical Characteristics Table 17 Parameter Timing Parameter by Speed Grade - DDR2-400B & DDR2-533C Symbol -3.7 DDR2-533 4-4-4 Min. DQS-DQ skew (for DQS & associated tDQSQ DQ signals) Write command to 1st DQS latching transition DQ and DM input setup time (differential data strobe) DQ and DM input setup time (single ended data strobe) DQS falling edge hold time from CK (write cycle) DQS falling edge to CK setup time (write cycle) Clock half period Data-out high-impedance time from CK / CK Address and control input hold time -- Max. 300 -5 DDR2-400 3-3-3 Min. -- Max. 350 ps Unit Notes1)
tDQSS
WL - 0.25 WL + 0.25 -- -- -- --
WL - 0.25 WL + 0.25 tCK 150 25 0.2 0.2 -- -- -- -- ps ps
tDS(base) 100 tDS1(base) -25 tDSH tDSS tHP tHZ
0.2 0.2
tCK tCK
MIN. (tCL, tCH) -- 375 0.6 250
MIN. (tCL, tCH) -- 475 0.6 350
tAC.MAX
-- -- --
tAC.MAX
-- -- --
ps ps
tIH(base) Address and control input pulse width tIPW
(each input) Address and control input setup time tIS(base) DQ low-impedance time from CK / CK tLZ(DQ) DQS low-impedance from CK / CK Mode register set command cycle time OCD drive mode output delay Data output hold time from DQS Data hold skew factor Average periodic refresh Interval
tCK
ps ps ps
2 x tAC.MIN tAC.MAX
2 x tAC.MIN tAC.MAX
tLZ(DQS) tMRD tOIT tQH tQHS tREFI
tAC.MIN
2 0
tAC.MAX
-- 12
tAC.MIN
2 0
tAC.MAX
-- 12 -- 450 7.8 3.9 --
tCK
ns
tHP - tQHS --
-- -- -- 75 400 7.8 3.9 -- -- 1.1 0.60 -- -- -- -- 0.60
tHPQ - tQHS
-- -- -- 75
ps
s s
ns ns
2) 3)
Auto-Refresh to Active/Auto-Refresh tRFC command period Precharge-All (4 banks) command period Read preamble Read postamble Active bank A to Active bank B command period
tRP tRPRE tRPST tRRD
tRP + 1tCK
0.9 0.40 7.5 10 7.5 0.35xtCK 0.40
tRP + 1tCK --
0.9 0.40 7.5 10 7.5 0.35xtCK 0.40 1.1 0.60 -- -- -- -- 0.60
tCK tCK
ns ns ns
Internal Read to Precharge command tRTP delay Write preamble Write postamble
tWPRE tWPST
tCK tCK
Data Sheet
28
Rev. 1.0, 2004-10 02182004-UN2L-F13U
HYS72T[32/64]0[0/2][0/1]HR-[3.7/5]-A Registered Double-Data-Rate-Two SDRAM Modules
Electrical Characteristics Table 17 Parameter Timing Parameter by Speed Grade - DDR2-400B & DDR2-533C Symbol -3.7 DDR2-533 4-4-4 Min. Write recovery time for write without Auto-Precharge Write recovery time for write with Auto-Precharge Internal Write to Read command delay Exit power down to any valid command (other than NOP or Deselect) Max. -- 15 -5 DDR2-400 3-3-3 Min. 15 Max. -- ns Unit Notes1)
tWR
WR
tWR/tCK
7.5 2 -- --
tWR/tCK
10 2 -- --
tCK
ns
tWTR tXARD
tCK tCK tCK
ns
Exit active power-down mode to Read tXARDS command (slow exit, lower power) Exit precharge power-down to any valid command (other than NOP or Deselect) Exit Self-Refresh to non-Read command Exit Self-Refresh to Read command
2) 0
6 - AL 2
-- --
6 - AL 2
-- --
tXP tXSNR tXSRD
tRFC +10
200
-- --
tRFC +10
200
-- --
tCK
1) For details and notes see the relevant INFINEON component data sheet
TCASE 85 C 3) 85 C < TCASE 95 C
ODT AC Electrical Characteristics and Operating Conditions Parameter / Condition ODT turn-on delay ODT turn-on ODT turn-on (Power-Down Modes) ODT turn-off delay ODT turn-off Values Min. Max. 2 2 Unit Notes
Table 18 Symbol
tAOND tAON tAONPD tAOFD tAOF tAOFPD tANPD tAXPD
tCK
ns ns
1)
tAC.MIN tAC.MAX + 1 ns tAC.MIN + 2 ns 2 tCK + tAC.MAX + 1 ns
2.5 2.5
tCK
2)
tAC.MIN tAC.MAX + 0.6 ns ns ODT turn-off (Power-Down Modes) tAC.MIN + 2 ns 2.5 tCK + tAC.MAX + 1 ns ns ODT to Power Down Mode Entry Latency 3 -- tCK ODT Power Down Exit Latency 8 -- tCK
1) ODT turn on time min. is when the device leaves high impedance and ODT resistance begins to turn on. ODT turn on time max is when the ODT resistance is fully on. Both are measure from tAOND. 2) ODT turn off time min. is when the device starts to turn off ODT resistance. ODT turn off time max is when the bus is in high impedance. Both are measured from tAOFD.
Data Sheet
29
Rev. 1.0, 2004-10 02182004-UN2L-F13U
HYS72T[32/64]0[0/2][0/1]HR-[3.7/5]-A Registered Double-Data-Rate-Two SDRAM Modules
SPD Codes
5
Table 19
SPD Codes
SPD Codes for HYS72T[32000/64001/64020]HR-3.7-A HYS72T32000HR-3.7-A HYS72T64001HR-3.7-A HYS72T64020HR-3.7-A 512 MB x72 2 Ranks (x8) PC2-4200R- 444 Rev. 1.1 HEX 80 08 08 0D 0A 61 48 00 05 3D 50 02 82 08 08 00 0C 04 38 00 01 05 01 3D 50 Rev. 1.0, 2004-10 02182004-UN2L-F13U
Product Type
Organization
256 MB x72 1 Rank (x8)
512 MB x72 1 Rank (x4) PC2-4200R- 444 Rev. 1.1 HEX 80 08 08 0D 0B 60 48 00 05 3D 50 02 82 04 04 00 0C 04 38 00 01 05 01 3D 50
Label Code JEDEC SPD Revision Byte# Description 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Programmed SPD Bytes in EEPROM Total number of Bytes in EEPROM Memory Type (DDR2) Number of Row Addresses Number of Column Addresses DIMM Rank and Stacking Information Data Width Not used Interface Voltage Level
PC2-4200R- 444 Rev. 1.1 HEX 80 08 08 0D 0A 60 48 00 05 3D 50 02 82 08 08 00 0C 04 38 00 01 04 01 3D 50
tCK @ CLMAX (Byte 18) [ns] tAC SDRAM @ CLMAX (Byte 18) [ns]
Error Correction Support (non-ECC, ECC) Refresh Rate and Type Primary SDRAM Width Error Checking SDRAM Width Not used Burst Length Supported Number of Banks on SDRAM Device Supported CAS Latencies DIMM Mechanical Characteristics DIMM Type Information DIMM Attributes Component Attributes
tCK @ CLMAX -1 (Byte 18) [ns] tAC SDRAM @ CLMAX -1 [ns]
30
Data Sheet
HYS72T[32/64]0[0/2][0/1]HR-[3.7/5]-A Registered Double-Data-Rate-Two SDRAM Modules
SPD Codes Table 19 SPD Codes for HYS72T[32000/64001/64020]HR-3.7-A (cont'd) HYS72T32000HR-3.7-A HYS72T64001HR-3.7-A HYS72T64020HR-3.7-A 512 MB x72 2 Ranks (x8) PC2-4200R- 444 Rev. 1.1 HEX 50 60 3C 1E 3C 2D 40 25 37 10 22 3C 1E 1E 00 00 3C 4B 80 1E 28 0F 55 82 36 1F 21 Rev. 1.0, 2004-10 02182004-UN2L-F13U
Product Type
Organization
256 MB x72 1 Rank (x8)
512 MB x72 1 Rank (x4) PC2-4200R- 444 Rev. 1.1 HEX 50 60 3C 1E 3C 2D 80 25 37 10 22 3C 1E 1E 00 00 3C 4B 80 1E 28 0F 55 82 36 1F 21
Label Code JEDEC SPD Revision Byte# Description 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51
PC2-4200R- 444 Rev. 1.1 HEX 50 60 3C 1E 3C 2D 40 25 37 10 22 3C 1E 1E 00 00 3C 4B 80 1E 28 0F 55 82 36 1F 21
tCK @ CLMAX -2 (Byte 18) [ns] tAC SDRAM @ CLMAX -2 [ns] tRP.MIN [ns] tRRD.MIN [ns] tRCD.MIN [ns] tRAS.MIN [ns]
Module Density per Rank
tAS.MIN and tCS.MIN [ns] tAH.MIN and tCH.MIN [ns] tDS.MIN [ns] tDH.MIN [ns] tWR.MIN [ns] tWTR..MIN [ns] tRTP..MIN [ns]
Analysis Characteristics
tRC and tRFC Extension tRC.MIN [ns] tRFC.MIN [ns] tCK.MAX [ns] tDQSQ.MAX [ns] tQHS.MAX [ns]
PLL Relock Time
TCASE.MAX Delta / T4R4W Delta
Psi(T-A) DRAM T0 (DT0) T2N (DT2N, UDIMM) or T2Q ( (DT2Q, RDIMM) T2P (DT2P)
Data Sheet
31
HYS72T[32/64]0[0/2][0/1]HR-[3.7/5]-A Registered Double-Data-Rate-Two SDRAM Modules
SPD Codes Table 19 SPD Codes for HYS72T[32000/64001/64020]HR-3.7-A (cont'd) HYS72T32000HR-3.7-A HYS72T64001HR-3.7-A HYS72T64020HR-3.7-A 512 MB x72 2 Ranks (x8) PC2-4200R- 444 Rev. 1.1 HEX 1D 28 14 2C 15 21 C4 8C 61 78 11 A9 C1 00 00 00 00 00 00 00 xx 37 32 54 36 34 30 Rev. 1.0, 2004-10 02182004-UN2L-F13U
Product Type
Organization
256 MB x72 1 Rank (x8)
512 MB x72 1 Rank (x4) PC2-4200R- 444 Rev. 1.1 HEX 1D 28 14 2C 15 21 C4 8C 61 78 11 E1 C1 00 00 00 00 00 00 00 xx 37 32 54 36 34 30
Label Code JEDEC SPD Revision Byte# Description 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 T3N (DT3N) T3P.fast (DT3P fast) T3P.slow (DT3P slow) T4R (DT4R) / T4R4W S Sign (DT4R4W) T5B (DT5B) T7 (DT7) Psi(ca) PLL Psi(ca) REG TPLL (DTPLL) TREG (DTREG) / Toggle Rate SPD Revision Checksum of Bytes 0-62 JEDEC ID Code of Infineon (1) JEDEC ID Code of Infineon (2) JEDEC ID Code of Infineon (3) JEDEC ID Code of Infineon (4) JEDEC ID Code of Infineon (5) JEDEC ID Code of Infineon (6) JEDEC ID Code of Infineon (7) JEDEC ID Code of Infineon (8) Module Manufacturer Location Product Type, Char 1 Product Type, Char 2 Product Type, Char 3 Product Type, Char 4 Product Type, Char 5 Product Type, Char 6
PC2-4200R- 444 Rev. 1.1 HEX 1D 28 14 2C 15 21 C4 8C 61 78 11 A7 C1 00 00 00 00 00 00 00 xx 37 32 54 33 32 30
Data Sheet
32
HYS72T[32/64]0[0/2][0/1]HR-[3.7/5]-A Registered Double-Data-Rate-Two SDRAM Modules
SPD Codes Table 19 SPD Codes for HYS72T[32000/64001/64020]HR-3.7-A (cont'd) HYS72T32000HR-3.7-A HYS72T64001HR-3.7-A HYS72T64020HR-3.7-A 512 MB x72 2 Ranks (x8) PC2-4200R- 444 Rev. 1.1 HEX 32 30 48 52 33 2E 37 41 20 20 20 20 1x xx xx xx xx xx xx xx 00 Rev. 1.0, 2004-10 02182004-UN2L-F13U
Product Type
Organization
256 MB x72 1 Rank (x8)
512 MB x72 1 Rank (x4) PC2-4200R- 444 Rev. 1.1 HEX 30 31 48 52 33 2E 37 41 20 20 20 20 1x xx xx xx xx xx xx xx 00
Label Code JEDEC SPD Revision Byte# Description 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 127 Product Type, Char 7 Product Type, Char 8 Product Type, Char 9 Product Type, Char 10 Product Type, Char 11 Product Type, Char 12 Product Type, Char 13 Product Type, Char 14 Product Type, Char 15 Product Type, Char 16 Product Type, Char 17 Product Type, Char 18 Module Revision Code Test Program Revision Code Module Manufacturing Date Year Module Manufacturing Date Week Module Serial Number (1) Module Serial Number (2) Module Serial Number (3) Module Serial Number (4) Not used
PC2-4200R- 444 Rev. 1.1 HEX 30 30 48 52 33 2E 37 41 20 20 20 20 1x xx xx xx xx xx xx xx 00
Data Sheet
33
HYS72T[32/64]0[0/2][0/1]HR-[3.7/5]-A Registered Double-Data-Rate-Two SDRAM Modules
SPD Codes
Table 20
SPD Codes for HYS72T[32000/64001/64020]HR-5-A HYS72T32000HR-5-A HYS72T64001HR-5-A HYS72T64020HR-5-A 512 MB x72 2 Ranks (x8) PC2-3200R- 333 Rev. 1.1 HEX 80 08 08 0D 0A 61 48 00 05 50 60 02 82 08 08 00 0C 04 38 00 01 05 01 50 60 50 60 Rev. 1.0, 2004-10 02182004-UN2L-F13U
Product Type
Organization
256 MB x72 1 Rank (x8)
512 MB x72 1 Rank (x4) PC2-3200R- 333 Rev. 1.1 HEX 80 08 08 0D 0B 60 48 00 05 50 60 02 82 04 04 00 0C 04 38 00 01 05 01 50 60 50 60
Label Code JEDEC SPD Revision Byte# Description 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 Programmed SPD Bytes in EEPROM Total number of Bytes in EEPROM Memory Type (DDR2) Number of Row Addresses Number of Column Addresses DIMM Rank and Stacking Information Data Width Not used Interface Voltage Level
PC2-3200R- 333 Rev. 1.1 HEX 80 08 08 0D 0A 60 48 00 05 50 60 02 82 08 08 00 0C 04 38 00 01 04 01 50 60 50 60
tCK @ CLMAX (Byte 18) [ns] tAC SDRAM @ CLMAX (Byte 18) [ns]
Error Correction Support (non-ECC, ECC) Refresh Rate and Type Primary SDRAM Width Error Checking SDRAM Width Not used Burst Length Supported Number of Banks on SDRAM Device Supported CAS Latencies DIMM Mechanical Characteristics DIMM Type Information DIMM Attributes Component Attributes
tCK @ CLMAX -1 (Byte 18) [ns] tAC SDRAM @ CLMAX -1 [ns] tCK @ CLMAX -2 (Byte 18) [ns] tAC SDRAM @ CLMAX -2 [ns]
34
Data Sheet
HYS72T[32/64]0[0/2][0/1]HR-[3.7/5]-A Registered Double-Data-Rate-Two SDRAM Modules
SPD Codes Table 20 SPD Codes for HYS72T[32000/64001/64020]HR-5-A (cont'd) HYS72T32000HR-5-A HYS72T64001HR-5-A HYS72T64020HR-5-A 512 MB x72 2 Ranks (x8) PC2-3200R- 333 Rev. 1.1 HEX 3C 1E 3C 28 40 35 47 15 27 3C 28 1E 00 00 37 4B 80 23 2D 0F 53 82 2E 19 21 19 20 14 Rev. 1.0, 2004-10 02182004-UN2L-F13U
Product Type
Organization
256 MB x72 1 Rank (x8)
512 MB x72 1 Rank (x4) PC2-3200R- 333 Rev. 1.1 HEX 3C 1E 3C 28 80 35 47 15 27 3C 28 1E 00 00 37 4B 80 23 2D 0F 53 82 2E 19 21 19 20 14
Label Code JEDEC SPD Revision Byte# Description 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54
PC2-3200R- 333 Rev. 1.1 HEX 3C 1E 3C 28 40 35 47 15 27 3C 28 1E 00 00 37 4B 80 23 2D 0F 53 82 2E 19 21 19 20 14 35
tRP.MIN [ns] tRRD.MIN [ns] tRCD.MIN [ns] tRAS.MIN [ns]
Module Density per Rank
tAS.MIN and tCS.MIN [ns] tAH.MIN and tCH.MIN [ns] tDS.MIN [ns] tDH.MIN [ns] tWR.MIN [ns] tWTR.MIN [ns] tRTP.MIN [ns]
Analysis Characteristics
tRC and tRFC Extension tRC.MIN [ns] tRFC.MIN [ns] tCK.MAX [ns] tDQSQ.MAX [ns] tQHS.MAX [ns]
PLL Relock Time
TCASE.MAX Delta / T4R4W Delta
Psi(T-A) DRAM T0 (DT0) T2N (DT2N, UDIMM) or T2Q ( (DT2Q, RDIMM) T2P (DT2P) T3N (DT3N) T3P.fast (DT3P fast) T3P.slow (DT3P slow)
Data Sheet
HYS72T[32/64]0[0/2][0/1]HR-[3.7/5]-A Registered Double-Data-Rate-Two SDRAM Modules
SPD Codes Table 20 SPD Codes for HYS72T[32000/64001/64020]HR-5-A (cont'd) HYS72T32000HR-5-A HYS72T64001HR-5-A HYS72T64020HR-5-A 512 MB x72 2 Ranks (x8) PC2-3200R- 333 Rev. 1.1 HEX 26 14 1F C4 8C 59 5C 11 DA C1 00 00 00 00 00 00 00 xx 37 32 54 36 34 30 32 30 48 52 Rev. 1.0, 2004-10 02182004-UN2L-F13U
Product Type
Organization
256 MB x72 1 Rank (x8)
512 MB x72 1 Rank (x4) PC2-3200R- 333 Rev. 1.1 HEX 26 14 1F C4 8C 59 5C 11 12 C1 00 00 00 00 00 00 00 xx 37 32 54 36 34 30 30 31 48 52
Label Code JEDEC SPD Revision Byte# Description 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 T4R (DT4R) / T4R4W S Sign (DT4R4W) T5B (DT5B) T7 (DT7) Psi(ca) PLL Psi(ca) REG TPLL (DTPLL) TREG (DTREG) / Toggle Rate SPD Revision Checksum of Bytes 0-62 JEDEC ID Code of Infineon (1) JEDEC ID Code of Infineon (2) JEDEC ID Code of Infineon (3) JEDEC ID Code of Infineon (4) JEDEC ID Code of Infineon (5) JEDEC ID Code of Infineon (6) JEDEC ID Code of Infineon (7) JEDEC ID Code of Infineon (8) Module Manufacturer Location Product Type, Char 1 Product Type, Char 2 Product Type, Char 3 Product Type, Char 4 Product Type, Char 5 Product Type, Char 6 Product Type, Char 7 Product Type, Char 8 Product Type, Char 9 Product Type, Char 10 36
PC2-3200R- 333 Rev. 1.1 HEX 26 14 1F C4 8C 59 5C 11 D8 C1 00 00 00 00 00 00 00 xx 37 32 54 33 32 30 30 30 48 52
Data Sheet
HYS72T[32/64]0[0/2][0/1]HR-[3.7/5]-A Registered Double-Data-Rate-Two SDRAM Modules
SPD Codes Table 20 SPD Codes for HYS72T[32000/64001/64020]HR-5-A (cont'd) HYS72T32000HR-5-A HYS72T64001HR-5-A HYS72T64020HR-5-A 512 MB x72 2 Ranks (x8) PC2-3200R- 333 Rev. 1.1 HEX 35 41 20 20 20 20 20 20 1x xx xx xx xx xx xx xx 00 Rev. 1.0, 2004-10 02182004-UN2L-F13U
Product Type
Organization
256 MB x72 1 Rank (x8)
512 MB x72 1 Rank (x4) PC2-3200R- 333 Rev. 1.1 HEX 35 41 20 20 20 20 20 20 1x xx xx xx xx xx xx xx 00
Label Code JEDEC SPD Revision Byte# Description 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 127 Product Type, Char 11 Product Type, Char 12 Product Type, Char 13 Product Type, Char 14 Product Type, Char 15 Product Type, Char 16 Product Type, Char 17 Product Type, Char 18 Module Revision Code Test Program Revision Code Module Manufacturing Date Year Module Manufacturing Date Week Module Serial Number (1) Module Serial Number (2) Module Serial Number (3) Module Serial Number (4) Not used
PC2-3200R- 333 Rev. 1.1 HEX 35 41 20 20 20 20 20 20 1x xx xx xx xx xx xx xx 00
Data Sheet
37
HYS72T[32/64]0[0/2][0/1]HR-[3.7/5]-A Registered Double-Data-Rate-Two SDRAM Modules
SPD Codes
Table 21
SPD Codes for HYS72T[64000/128000/128020]HR-5-A HYS72T128000HR-5-A HYS72T128020HR-5-A 1 GByte x72 2 Ranks (x8) Rev. 1.1 HEX 80 08 08 0E 0A 61 48 00 05 50 60 02 82 08 08 00 0C 04 38 00 01 05 01 50 60 50 60 3C Rev. 1.0, 2004-10 02182004-UN2L-F13U HYS72T64000HR-5-A 512 MB x72 1 Rank (x8)
Product Type
Organization
1 GByte x72 1 Rank (x4) Rev. 1.1 HEX 80 08 08 0E 0B 60 48 00 05 50 60 02 82 04 04 00 0C 04 38 00 01 05 01 50 60 50 60 3C
Label Code JEDEC SPD Revision Byte# Description 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 Programmed SPD Bytes in EEPROM Total number of Bytes in EEPROM Memory Type (DDR2) Number of Row Addresses Number of Column Addresses DIMM Rank and Stacking Information Data Width Not used Interface Voltage Level
PC2-3200R-333 PC2-3200R-333 PC2-3200R-333 Rev. 1.1 HEX 80 08 08 0E 0A 60 48 00 05 50 60 02 82 08 08 00 0C 04 38 00 01 04 01 50 60 50 60 3C 38
tCK @ CLMAX (Byte 18) [ns] tAC SDRAM @ CLMAX (Byte 18) [ns]
Error Correction Support (non-ECC, ECC) Refresh Rate and Type Primary SDRAM Width Error Checking SDRAM Width Not used Burst Length Supported Number of Banks on SDRAM Device Supported CAS Latencies DIMM Mechanical Characteristics DIMM Type Information DIMM Attributes Component Attributes
tCK @ CLMAX -1 (Byte 18) [ns] tAC SDRAM @ CLMAX -1 [ns] tCK @ CLMAX -2 (Byte 18) [ns] tAC SDRAM @ CLMAX -2 [ns] tRP.MIN [ns]
Data Sheet
HYS72T[32/64]0[0/2][0/1]HR-[3.7/5]-A Registered Double-Data-Rate-Two SDRAM Modules
SPD Codes Table 21 SPD Codes for HYS72T[64000/128000/128020]HR-5-A (cont'd) HYS72T128000HR-5-A HYS72T128020HR-5-A 1 GByte x72 2 Ranks (x8) Rev. 1.1 HEX 1E 3C 28 80 35 47 15 27 3C 28 1E 00 00 37 69 80 23 2D 0F 51 78 32 1D 1E 1B 1E 17 28 Rev. 1.0, 2004-10 02182004-UN2L-F13U HYS72T64000HR-5-A 512 MB x72 1 Rank (x8) Label Code JEDEC SPD Revision Byte# Description 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 Rev. 1.1 HEX 1E 3C 28 80 35 47 15 27 3C 28 1E 00 00 37 69 80 23 2D 0F 51 78 32 1E 1B 1E 17 28
Product Type
Organization
1 GByte x72 1 Rank (x4) Rev. 1.1 HEX 1E 3C 28 01 35 47 15 27 3C 28 1E 00 00 37 69 80 23 2D 0F 51 78 32 1D 1E 1B 1E 17 28
PC2-3200R-333 PC2-3200R-333 PC2-3200R-333
tRRD.MIN [ns] tRCD.MIN [ns] tRAS.MIN [ns]
Module Density per Rank
tAS.MIN and tCS.MIN [ns] tAH.MIN and tCH.MIN [ns] tDS.MIN [ns] tDH.MIN [ns] tWR.MIN [ns] tWTR.MIN [ns] tRTP.MIN [ns]
Analysis Characteristics
tRC and tRFC Extension tRC.MIN [ns] tRFC.MIN [ns] tCK.MAX [ns] tDQSQ.MAX [ns] tQHS.MAX [ns]
PLL Relock Time
TCASE.MAX Delta / T4R4W Delta
Psi(T-A) DRAM T0 (DT0) T2P (DT2P) T3N (DT3N) T3P.fast (DT3P fast) T3P.slow (DT3P slow) T4R (DT4R) / T4R4W S Sign (DT4R4W)
T2N (DT2N, UDIMM) or T2Q ( (DT2Q, RDIMM) 1D
Data Sheet
39
HYS72T[32/64]0[0/2][0/1]HR-[3.7/5]-A Registered Double-Data-Rate-Two SDRAM Modules
SPD Codes Table 21 SPD Codes for HYS72T[64000/128000/128020]HR-5-A (cont'd) HYS72T128000HR-5-A HYS72T128020HR-5-A 1 GByte x72 2 Ranks (x8) Rev. 1.1 HEX 1B 1E C4 8C 59 5C 11 3D C1 00 00 00 00 00 00 00 xx 37 32 54 31 32 38 30 32 30 48 52 Rev. 1.0, 2004-10 02182004-UN2L-F13U HYS72T64000HR-5-A 512 MB x72 1 Rank (x8) Label Code JEDEC SPD Revision Byte# Description 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 T5B (DT5B) T7 (DT7) Psi(ca) PLL Psi(ca) REG TPLL (DTPLL) TREG (DTREG) / Toggle Rate SPD Revision Checksum of Bytes 0-62 JEDEC ID Code of Infineon (1) JEDEC ID Code of Infineon (2) JEDEC ID Code of Infineon (3) JEDEC ID Code of Infineon (4) JEDEC ID Code of Infineon (5) JEDEC ID Code of Infineon (6) JEDEC ID Code of Infineon (7) JEDEC ID Code of Infineon (8) Module Manufacturer Location Product Type, Char 1 Product Type, Char 2 Product Type, Char 3 Product Type, Char 4 Product Type, Char 5 Product Type, Char 6 Product Type, Char 7 Product Type, Char 8 Product Type, Char 9 Product Type, Char 10 Product Type, Char 11 Rev. 1.1 HEX 1B 1E C4 8C 59 5C 11 3B C1 00 00 00 00 00 00 00 xx 37 32 54 36 34 30 30 30 48 52 35
Product Type
Organization
1 GByte x72 1 Rank (x4) Rev. 1.1 HEX 1B 1E C4 8C 59 5C 11 B6 C1 00 00 00 00 00 00 00 xx 37 32 54 31 32 38 30 30 30 48 52
PC2-3200R-333 PC2-3200R-333 PC2-3200R-333
Data Sheet
40
HYS72T[32/64]0[0/2][0/1]HR-[3.7/5]-A Registered Double-Data-Rate-Two SDRAM Modules
SPD Codes Table 21 SPD Codes for HYS72T[64000/128000/128020]HR-5-A (cont'd) HYS72T128000HR-5-A HYS72T128020HR-5-A 1 GByte x72 2 Ranks (x8) Rev. 1.1 HEX 35 41 20 20 20 20 20 2x xx xx xx xx xx xx xx 00 Rev. 1.0, 2004-10 02182004-UN2L-F13U HYS72T64000HR-5-A 512 MB x72 1 Rank (x8) Label Code JEDEC SPD Revision Byte# Description 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 127 Product Type, Char 12 Product Type, Char 13 Product Type, Char 14 Product Type, Char 15 Product Type, Char 16 Product Type, Char 17 Product Type, Char 18 Module Revision Code Test Program Revision Code Module Manufacturing Date Year Module Manufacturing Date Week Module Serial Number (1) Module Serial Number (2) Module Serial Number (3) Module Serial Number (4) Not used Rev. 1.1 HEX 41 20 20 20 20 20 20 2x xx xx xx xx xx xx xx 00
Product Type
Organization
1 GByte x72 1 Rank (x4) Rev. 1.1 HEX 35 41 20 20 20 20 20 2x xx xx xx xx xx xx xx 00
PC2-3200R-333 PC2-3200R-333 PC2-3200R-333
Data Sheet
41
HYS72T[32/64]0[0/2][0/1]HR-[3.7/5]-A Registered Double-Data-Rate-Two SDRAM Modules
SPD Codes
Table 22
SPD Codes for HYS72T[256020/256220]HR-5-A HYS72T256020HR-5-A HYS72T256220HR-5-A 2 GByte x72 2 Ranks (x4) PC2-3200R-333 Rev. 1.1 HEX 80 08 08 0E 0B 61 48 00 05 50 60 02 82 04 04 00 0C 04 38 00 01 07 01 50 60 50 60 3C Rev. 1.0, 2004-10 02182004-UN2L-F13U
Product Type
Organization
2 GByte x72 2 Ranks (x4)
Label Code JEDEC SPD Revision Byte# Description 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 Programmed SPD Bytes in EEPROM Total number of Bytes in EEPROM Memory Type (DDR2) Number of Row Addresses Number of Column Addresses DIMM Rank and Stacking Information Data Width Not used Interface Voltage Level
PC2-3200R-333 Rev. 1.1 HEX 80 08 08 0E 0B 61 48 00 05 50 60 02 82 04 04 00 0C 04 38 00 01 07 01 50 60 50 60 3C 42
tCK @ CLMAX (Byte 18) [ns] tAC SDRAM @ CLMAX (Byte 18) [ns]
Error Correction Support (non-ECC, ECC) Refresh Rate and Type Primary SDRAM Width Error Checking SDRAM Width Not used Burst Length Supported Number of Banks on SDRAM Device Supported CAS Latencies DIMM Mechanical Characteristics DIMM Type Information DIMM Attributes Component Attributes
tCK @ CLMAX -1 (Byte 18) [ns] tAC SDRAM @ CLMAX -1 [ns] tCK @ CLMAX -2 (Byte 18) [ns] tAC SDRAM @ CLMAX -2 [ns] tRP.MIN [ns]
Data Sheet
HYS72T[32/64]0[0/2][0/1]HR-[3.7/5]-A Registered Double-Data-Rate-Two SDRAM Modules
SPD Codes Table 22 SPD Codes for HYS72T[256020/256220]HR-5-A (cont'd) HYS72T256020HR-5-A HYS72T256220HR-5-A 2 GByte x72 2 Ranks (x4) PC2-3200R-333 Rev. 1.1 HEX 1E 3C 28 01 35 47 15 27 3C 28 1E 00 00 37 69 80 23 2D 0F 51 78 32 1D 1E 1B 1E 17 28 Rev. 1.0, 2004-10 02182004-UN2L-F13U
Product Type
Organization
2 GByte x72 2 Ranks (x4)
Label Code JEDEC SPD Revision Byte# Description 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
PC2-3200R-333 Rev. 1.1 HEX 1E 3C 28 01 35 47 15 27 3C 28 1E 00 00 37 69 80 23 2D 0F 51 78 32 1D 1E 1B 1E 17 28
tRRD.MIN [ns] tRCD.MIN [ns] tRAS.MIN [ns]
Module Density per Rank
tAS.MIN and tCS.MIN [ns] tAH.MIN and tCH.MIN [ns] tDS.MIN [ns] tDH.MIN [ns] tWR.MIN [ns] tWTR.MIN [ns] tRTP.MIN [ns]
Analysis Characteristics
tRC and tRFC Extension tRC.MIN [ns] tRFC.MIN [ns] tCK.MAX [ns] tDQSQ.MAX [ns] tQHS.MAX [ns]
PLL Relock Time
TCASE.MAX Delta / T4R4W Delta
Psi(T-A) DRAM T0 (DT0) T2N (DT2N, UDIMM) or T2Q ( (DT2Q, RDIMM) T2P (DT2P) T3N (DT3N) T3P.fast (DT3P fast) T3P.slow (DT3P slow) T4R (DT4R) / T4R4W S Sign (DT4R4W)
Data Sheet
43
HYS72T[32/64]0[0/2][0/1]HR-[3.7/5]-A Registered Double-Data-Rate-Two SDRAM Modules
SPD Codes Table 22 SPD Codes for HYS72T[256020/256220]HR-5-A (cont'd) HYS72T256020HR-5-A HYS72T256220HR-5-A 2 GByte x72 2 Ranks (x4) PC2-3200R-333 Rev. 1.1 HEX 1B 1E C4 8C 59 5C 11 B9 C1 00 00 00 00 00 00 00 xx 37 32 54 32 35 36 32 32 30 48 52 Rev. 1.0, 2004-10 02182004-UN2L-F13U
Product Type
Organization
2 GByte x72 2 Ranks (x4)
Label Code JEDEC SPD Revision Byte# Description 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 T5B (DT5B) T7 (DT7) Psi(ca) PLL Psi(ca) REG TPLL (DTPLL) TREG (DTREG) / Toggle Rate SPD Revision Checksum of Bytes 0-62 JEDEC ID Code of Infineon (1) JEDEC ID Code of Infineon (2) JEDEC ID Code of Infineon (3) JEDEC ID Code of Infineon (4) JEDEC ID Code of Infineon (5) JEDEC ID Code of Infineon (6) JEDEC ID Code of Infineon (7) JEDEC ID Code of Infineon (8) Module Manufacturer Location Product Type, Char 1 Product Type, Char 2 Product Type, Char 3 Product Type, Char 4 Product Type, Char 5 Product Type, Char 6 Product Type, Char 7 Product Type, Char 8 Product Type, Char 9 Product Type, Char 10 Product Type, Char 11
PC2-3200R-333 Rev. 1.1 HEX 1B 1E C4 8C 59 5C 11 B9 C1 00 00 00 00 00 00 00 xx 37 32 54 32 35 36 30 32 30 48 52
Data Sheet
44
HYS72T[32/64]0[0/2][0/1]HR-[3.7/5]-A Registered Double-Data-Rate-Two SDRAM Modules
SPD Codes Table 22 SPD Codes for HYS72T[256020/256220]HR-5-A (cont'd) HYS72T256020HR-5-A HYS72T256220HR-5-A 2 GByte x72 2 Ranks (x4) PC2-3200R-333 Rev. 1.1 HEX 35 41 20 20 20 20 20 2x xx xx xx xx xx xx xx 00 Rev. 1.0, 2004-10 02182004-UN2L-F13U
Product Type
Organization
2 GByte x72 2 Ranks (x4)
Label Code JEDEC SPD Revision Byte# Description 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 127 Product Type, Char 12 Product Type, Char 13 Product Type, Char 14 Product Type, Char 15 Product Type, Char 16 Product Type, Char 17 Product Type, Char 18 Module Revision Code Test Program Revision Code Module Manufacturing Date Year Module Manufacturing Date Week Module Serial Number (1) Module Serial Number (2) Module Serial Number (3) Module Serial Number (4) Not used
PC2-3200R-333 Rev. 1.1 HEX 35 41 20 20 20 20 20 2x xx xx xx xx xx xx xx 00
Data Sheet
45
HYS72T[32/64]0[0/2][0/1]HR-[3.7/5]-A Registered Double-Data-Rate-Two SDRAM Modules
Package Outlines
6
0.1 A B C
Package Outlines
133.35 128.95 2.7 MAX.
4
4x
1
4 2.5 5 63 55
120 C 0.4
30
1.27 0.1
1.5 0.1
3.8
121
240
2.3 0.1 10
A
(3)
Detail of contacts
0.2
1
0.8 0.05
2.5 0.2
0.1 A B C
Burr max. 0.4 allowed
Figure 5
Package Outline Raw Card F L-DIM-240-11
Data Sheet
46
Rev. 1.0, 2004-10 02182004-UN2L-F13U
17.8
B
GLD09655
HYS72T[32/64]0[0/2][0/1]HR-[3.7/5]-A Registered Double-Data-Rate-Two SDRAM Modules
Package Outlines
0.1 A B C
133.35 128.95 4 MAX.
4
4x
1
4 2.5 5 63 55
120 C 0.4
30
1.27 0.1
1.5 0.1
3.8
121
240
2.3 0.1 10
A
(3)
Detail of contacts
0.2
1
0.8 0.05
2.5 0.2
0.1 A B C
Burr max. 0.4 allowed
Figure 6
Package Outline Raw Card G L-DIM-240-12
Data Sheet
47
Rev. 1.0, 2004-10 02182004-UN2L-F13U
17.8
B
GLD09656
HYS72T[32/64]0[0/2][0/1]HR-[3.7/5]-A Registered Double-Data-Rate-Two SDRAM Modules
Package Outlines
0.1 A B C
133.35 128.95 4 MAX.
4
4x
1
4 2.5 5 63 55
120 C 0.4
30
1.27 0.1
1.5 0.1
3.8
121
240
2.3 0.1 10
A
(3)
Detail of contacts
0.2
1
0.8 0.05
2.5 0.2
0.1 A B C
Burr max. 0.4 allowed
Figure 7
Package Outline Raw Card H L-DIM-240-13
Data Sheet
48
Rev. 1.0, 2004-10 02182004-UN2L-F13U
17.8
B
GLD09657
HYS72T[32/64]0[0/2][0/1]HR-[3.7/5]-A Registered Double-Data-Rate-Two SDRAM Modules
Product Type Nomenclature (DDR2 DRAMs and DIMMs)
7
Product Type Nomenclature (DDR2 DRAMs and DIMMs)
Infineon's nomenclature uses simple coding combined with some propriatory coding. Table 23 provides examples for module and component product type number as well as the field number. The detailed field description together with possible values and coding explanation is listed for modules in Table 24 and for components in Table 25. Table 23 Nomenclature Fields and Examples Field Number 1 Micro-DIMM DDR2 DRAM Table 24 1 2 3 4 HYS HYB 2 64 18 3 T T 4 64 512 5 0 16 6 2 7 0 0 8 K A 9 M C 10 -5 -5 11 -A
Example for
DDR2 DIMM Nomenclature Values Coding HYS 64 72 T 32 64 128 256 0 .. 9 Constant Non-ECC ECC DDR2 256 MByte 512 MByte 1 GByte 2 GByte look up table 1, 2, 4 look up table look up table SO-DIMM Micro-DIMM Registered Unbuffered PC2-4200 4-4-4 PC2-3200 3-3-3 First Second
Field Description INFINEON Modul Prefix Module Data Width [bit] DRAM Technology Memory Density per I/O [Mbit]; Module Density1)
1) Multiplying "Memory Density per I/O" with "Module Data Width" and dividing by 8 for Non-ECC and 9 for ECC modules gives the overall module memory density in MBytes as listed in column "Coding".
Table 25 1 2 3 4
DDR2 DRAM Nomenclature Values Coding HYB Constant SSTL1.8 DDR2 256 Mbit 512 Mbit 1 Gbit 2 Gbit x4 x8 x16 look up table First Second FBGA, lead-containing FBGA, lead-free DDR2-533C DDR2-400B
Field Description INFINEON Component Prefix DRAM Technology
Interface Voltage [V] 18 T Component Density 256 [Mbit] 512 1G 2G
5 6 7 8 9
Raw Card Generation
Number of Module 0, 2, 4 Ranks Product Variations 0 .. 9 Package, Lead-Free Status Module Type A .. Z D M R U
5+6 Number of I/Os
40 80 16
7 8 9
Product Variations Die Revision Package, Lead-Free Status Speed Grade N/A for Components
0 .. 9 A B C F
10 11
Speed Grade Die Revision
-3.7 -5 -A -B
10 11
-3.7 -5
Data Sheet
49
Rev. 1.0, 2004-10 02182004-UN2L-F13U
www.infineon.com
Published by Infineon Technologies AG

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